The present invention relates to fin formation in fin field-effect transistors (finFETs), and more specifically, to forming fins of differing heights in finFETs.
Field-effect transistors (FETs) generate an electric field, by a gate structure, to control the conductivity of a channel between source and drain structures in a semiconductor substrate. The source and drain structures may be formed by doping the semiconductor substrate, a channel region may extend between the source and the drain on the semiconductor substrate and the gate may be formed on the semiconductor substrate between the source and drain regions.
Dimensions of finFET devices may be limited by various design considerations including available geographical space in a circuit for the finFET device and required ratios of various devices in the circuit. For example, in a static random access memory (SRAM) device, pull-up and pull-down devices must have widths (corresponding to heights in finFET devices) of predetermined ratios with respect to each other. However, the device width for a finFET device is determined by the number of fins multiplied by a fin height. Since the number of fins may be limited due to constraints on the size of the finFET circuit, the device width ratio may be limited for fins with only height.
Typically, different device widths are obtained by using different numbers of fins in different finFETs. In some designs, it is desirable to change an active area of the fins to increase performance of the finFET. For example, in a static random access memory (SRAM) design, a p-type FET (PFET) having a smaller active area is desired to obtain a weaker PFET, which increases device stability. However, since typical PFET designs use only one fin, the number of fins may not be reduced to decrease the active area of the fins.